n.每十人殺一人者；殺害多數(shù)人者

Design of a digital decimator of sigma-delta ADC is discussed. 本文主要論述了用于音頻系統(tǒng)ADC的過(guò)采樣抽取濾波器的設(shè)計(jì)。

It consists of an analog modulator and a digital decimator. 它由一個(gè)模擬的調(diào)制器和一個(gè)數(shù)字降采樣濾波器組成。

The deta-sigma ADC is composed of analog deta-sigma modulator and decimator. 模擬過(guò)采樣調(diào)制器還可以應(yīng)用于處理音頻信號(hào)的D類功率放大器中。

At last, this design of the decimator is implemented on FPGA hardware platform, and tested by oscilloscope and spectrum analyzer. 最后，采用系統(tǒng)硬件平臺(tái)將程序?qū)懭隖PGA芯片，利用示波器和頻譜分析儀對(duì)設(shè)計(jì)的抽取器進(jìn)行了頻域和時(shí)域性能分析。

The main blocks are CIC anti-alias filter, decimator, DC canceller, Iterative multiplier, half-band filter, IIR low pass filter, DDS etc. 系統(tǒng)主要模塊包括：CIC抗混疊濾波器、抽取器、去直流偏置、疊代式乘法器、半帶濾波器、IIR低通濾波器、數(shù)字頻率轉(zhuǎn)換器等。