n.自測(cè)試
In this paper, based on the build-in self-test for logic circuits, a new approach is proposed to reduce pseudorandom test sequence length. 本文建立在邏輯電路內(nèi)部自測(cè)試的基礎(chǔ)上，提出了一種新的縮短偽隨機(jī)測(cè)試序列長(zhǎng)度的方法。
